This application relates to characterization of structures fabricated on plate substrates including but not limited to integrated structures featuring one or more thin-film layers or graded layers.
Substrates formed of suitable solid-state materials may be used as platforms to support various structures, such as layered or graded panels, and multilevel, thin film microstructures deposited on the substrates. Integrated electronic circuits, integrated optical devices and opto-electronic circuits, micro-electro-mechanical systems (MEMS) deposited on wafers, three-dimensional electronic circuits, system-on-chip structures, lithographic reticles, and flat panel display systems (e.g., LCD and plasma displays) are examples of such structures integrated on various types of plate substrates. Substrates may be made of semiconductor materials (e.g., silicon wafers), silicon on insulator wafers (SOIs), amorphous or glass materials, polymeric or organic materials, and others. Different thin material layers or different structures may be formed on the same substrate in these structures and are in contact with one another to form various interfaces with adjacent structures and with the substrate. Some devices may use complex multilayer or continuously graded geometries. In addition, some devices may form various three dimensional structures.
The above and other structures on substrates may be made from a multiplicity of fabrication and processing steps and thus may experience stresses caused by these steps, such as deposition or thermal stresses. Examples of known phenomena and processes that build up stresses in thin films include but are not limited to, lattice mismatch, chemical reactions, doping by, e.g., diffusion or implantation, rapid deposition by evaporation or sputtering, and material removal (e.g. CMP or etch). As another example, a metallization process in fabricating integrated circuits may produce multiple layers on a semiconductor substrate (e.g., silicon), often at elevated temperatures. The multiple layers may include a mixture of metal and dielectric films which usually exhibit different mechanical, physical and thermal properties from those of the underlying substrate or wafer. Hence, such multiple layers can lead to high stresses in the film layers in the interconnection structures. These stresses can cause undesired stress-induced voiding in the metal interconnects and are directly related to electromigration. In addition, the stresses may cause cracking of some films and even delamination between various film layers, between interconnects and the encapsulating dielectrics, and between the films and the substrate. It is known that metal voiding, electromigration, cracking and delamination are among the leading causes for loss of subsequent process yield and failures in integrated circuits. Therefore, these and other stresses may adversely affect the structural integrity and operations of the structures or devices, and the lifetimes of such structures or devices. Hence, the identification of the origins of the stress build-up, the accurate measurement and analysis of stresses, and the acquisition of information on the spatial distribution of such stresses are important in designing and processing the structures or devices and to improving the reliability and manufacturing yield of various layered structures.
Stresses in layered thin-film structures deposited on plate substrates may be calculated from the substrate curvature or “bow” based on a correlation between changes in the curvature and stress changes at the same location. Early attempts to provide such correlation are well known. Various formulations have been developed for measurements of stresses in thin films and most of these formulations are essentially based on extensions of Stoney's approximate plate analysis published in Proceedings of the Royal Society, London, Series A, vol. 82, pp. 172(1909). Stoney used a plate system with a stress bearing, relatively thin film deposited on a relatively thick substrate and derived a simple relation between the curvature of the plate system and the film stress at the same location based on a linear elasticity for small deformations and deflections. Stoney's formula also assumed film stresses and curvatures to be equi-biaxial (i.e., the same in all directions) and spatially constant (i.e., do not change with position) across the plate's surface.
Despite the explicit assumption of spatial uniformity in stress and curvature, the Stoney formula has often, arbitrarily, been applied to plate systems where this assumption was violated. As an example, the Stoney formula was applied in a “pointwise” manner in plate systems where the stress and curvature are known to vary with position. Such a localized application of the Stoney formula was used to extract a “local” value of stress from a “local” value of curvature. Based on this “liberal” interpretation of Stoney's formula, if the curvature component at any one location of a substrate can be measured, then the film stress at that same location can also be inferred.